Concurrent Algorithm and Hardware Implementation for Low-Latency Turbo Decoder Using a Single MAP Decoder

Ya-Cheng LU  Erl-Huei LU  

Publication
IEICE TRANSACTIONS on Communications   Vol.E93-B   No.1   pp.1-8
Publication Date: 2010/01/01
Online ISSN: 1745-1345
DOI: 10.1587/transcom.E93.B.1
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Fundamental Theories for Communications
Keyword: 
concurrent decoding,  turbo codes,  maximum a posteriori (MAP),  iterative decoding delay,  low latency,  

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Summary: 
In order to reduce the iterative decoding delay of convolutional turbo codes, this paper presents a concurrent decoding algorithm for the hardware implementation of turbo convolutional decoders. Different than a general turbo code, the hardware turbo decoder based on the proposed algorithm can update the priori information of message for each component code in a bit-by-bit manner as soon as it is generated by the other component code. The two component codes in a turbo code can thus be decoded concurrently, by using a single MAP decoder, subsequently reducing the decoding latency by approximately half while maintaining the bit error rate performance and a comparable hardware complexity, as a general turbo decoder.