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An Efficient LDPC Decoder Architecture with a HighPerformance Decoding Algorithm
JuiHui HUNG SauGee CHEN
Publication
IEICE TRANSACTIONS on Communications
Vol.E93B
No.11
pp.29802989 Publication Date: 2010/11/01
Online ISSN: 17451345
DOI: 10.1587/transcom.E93.B.2980
Print ISSN: 09168516 Type of Manuscript: PAPER Category: Fundamental Theories for Communications Keyword: channel coding, LDPC, decoder, algorithm, hardware,
Full Text: PDF>>
Summary:
In this work, a high performance LDPC decoder architecture is presented. It is a partiallyparallel architecture for lowcomplexity consideration. In order to eliminate the idling time and hardware complexity in conventional partiallyparallel decoders, the decoding process, decoder architecture and memory structure are optimized. Particularly, the paritycheck matrix is optimally partitioned into four unequal submatrices that lead to high efficiency in hardware sharing. As a result, it can handle two different codewords simultaneously with 100% hardware utilization. Furthermore, for minimizing the performance loss due to roundoff errors in fixedpoint implementations, the wellknown modified minsum decoding algorithm is enhanced by our recently proposed highperformance CMVP decoding algorithm. Overall, the proposed decoder has high throughput, low complexity, and good BER performances. In the circuit implementation example of the (576,288) parity check matrix for IEEE 802.16e standard, the decoder achieves a data rate of 5.5 Gbps assuming 10 decoding iterations and 7 quantization bits, with a small area of 653 K gates, based on UMC 90 nm process technology.

