For Full-Text PDF, please login, if you are a member of IEICE,|
or go to Pay Per View on menu list, if you are a nonmember of IEICE.
A New LDMOS Transistor Macro-Modeling for Accurately Predicting Bias Dependence of Gate-Overlap Capacitance
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/09/01
Online ISSN: 1745-1337
Print ISSN: 0916-8508
Type of Manuscript: PAPER
Category: VLSI Design Technology and CAD
LDMOS, macro model, gate-overlap capacitance, circuit simulation,
Full Text: PDF>>
We have developed a macro model, which allows us to describe precise LDMOS DC/AC characteristics. Characterization of anomalous gate input capacitance is the key issue in the LDMOS model development. We have newly employed a T-type distributed RC scheme for gate overlapped LDMOS drift region. The bias dependent resistance and capacitance are modeled independently in Verilog-A as R-model and PMOS-capacitance. The dividing factor of the distributed R is introduced to reflect the shield effect of the gate overlap capacitance. Comparison between the new model and measurement results has proven that the developed macro model reproduces accurately not only the gate input capacitance, but also DC characteristics.