A Bandwidth Optimized, 64 Cycles/MB Joint Parameter Decoder Architecture for Ultra High Definition H.264/AVC Applications

Jinjia ZHOU
Dajiang ZHOU
Xun HE
Satoshi GOTO

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E93-A    No.8    pp.1425-1433
Publication Date: 2010/08/01
Online ISSN: 1745-1337
DOI: 10.1587/transfun.E93.A.1425
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on Signal Processing)
Category: VLSI Design Technology and CAD
motion vector derivation,  DRAM bandwidth,  ultra high resolution,  video decoder,  H.264/AVC,  

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In this paper, VLSI architecture of a joint parameter decoder is proposed to realize the calculation of motion vector (MV), intra prediction mode (IPM) and boundary strength (BS) for ultra high definition H.264/AVC applications. For this architecture, a 64-cycle-per-MB pipeline with simplified control modes is designed to increase system throughput and reduce hardware cost. Moreover, in order to save memory bandwidth, the data which includes the motion information for the co-located picture and the last decoded line, is pre-processed before being stored to DRAM. A partition based storage format is applied to condense the MB level data, while variable length coding based compression method is utilized to reduce the data size in each partition. Experimental results show our design is capable of real-time 38402160@60 fps decoding at less than 133 MHz, with 37.2 k logic gates. Meanwhile, by applying the proposed scheme, 85-98% bandwidth saving is achieved, compared with storing the original information for every 44 block to DRAM.