A Processor Accelerator for Software Decoding of BCH Codes

Kazuhito ITO  

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E93-A   No.7   pp.1329-1337
Publication Date: 2010/07/01
Online ISSN: 1745-1337
DOI: 10.1587/transfun.E93.A.1329
Print ISSN: 0916-8508
Type of Manuscript: PAPER
Category: VLSI Design Technology and CAD
Keyword: 
error correction code,  BCH,  accelerator,  pipelining,  

Full Text: PDF(841.7KB)>>
Buy this Article




Summary: 
The BCH code is one of the well-known error correction codes and its decoding contains many operations in Galois field. These operations require many instruction steps or large memory area for look-up tables on ordinary processors. While dedicated hardware BCH decoders achieves higher decoding speed than software, the advantage of software decoding is its flexibility to decode BCH codes of variable parameters. In this paper, an auxiliary circuit to be embedded in a pipelined processor is proposed which accelerates software decoding of various BCH codes.