IEICE Trans - Low Power Pulse Generator Design Using Hybrid Logic

Low Power Pulse Generator Design Using Hybrid Logic

Jin-Fa LIN
Yin-Tsung HWANG
Ming-Hwa SHEU

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Vol.E93-A No.6 pp.1266-1268
Publication Date: 2010/06/01
Online ISSN: 1745-1337
DOI: 10.1587/transfun.E93.A.1266
Print ISSN: 0916-8508
Type of Manuscript: LETTER
Category: Circuit Theory
Keyword:
pulse generator, Flip-Flop, hybrid logic,

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Summary:
A low power pulse generator design using hybrid logic realization of a 3-input NAND gate is presented. The hybrid logic approach successfully shortens the critical path along the discharging transistor stack and thus reduces the short circuit power consumption during the pulse generation. The combination of pass transistor and full CMOS logic styles in one NAND gate design also helps minimize the required transistor size, which alleviates the loading capacitance of clock tree as well. Simulation results reveal that, compared with prior work, our design can achieve 20.5% and 23% savings respectively in power and circuit area.