Modeling of Power Noise Generation in Standard-Cell Based CMOS Digital Circuits

Tetsuro MATSUNO  Daisuke KOSAKA  Makoto NAGATA  

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E93-A   No.2   pp.440-447
Publication Date: 2010/02/01
Online ISSN: 1745-1337
DOI: 10.1587/transfun.E93.A.440
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
substrate noise,  power supply noise,  signal integrity,  substrate coupling,  power integrity,  

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Capacitance charging modeling efficiently captures power supply currents in dynamic operations of a CMOS digital circuit and accurately expresses their interaction with on- and off-chip impedance networks. Derivation of such models is generally defined for combinational and sequential logic functions. Simulated substrate and power noises due to sequential logic operation show clear dependency on the size of circuits as well as the internal activity of logic gates. Furthermore, it is experimentally found that the inclusion of impedance networks of a silicon substrate, a package, and an evaluation board, is substantially effective to improve the accuracy of noise analysis. Quantitative correlation among simulation with on-chip noise measurements is demonstrated in a 90-nm 1.2-V CMOS technology.