IEICE Trans - The Optimum Design Methodology of Low-Phase-Noise LC-VCO Using Multiple-Divide Technique

The Optimum Design Methodology of Low-Phase-Noise LC-VCO Using Multiple-Divide Technique

Shoichi HARA  Rui MURAKAMI  Kenichi OKADA  Akira MATSUZAWA

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E93-A    No.2    pp.424-430
Publication Date: 2010/02/01
Online ISSN: 1745-1337
DOI: 10.1587/transfun.E93.A.424
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
Category:
Keyword:
CMOS,  VCO,  divider,  inductor,

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Summary:
The multiple-divide technique, using the multi-ratio frequency divider, has a possibility to improve FoM of VCO. This paper proposes a design optimization of LC-VCO using the multiple-divide technique. In the simulated results using 90-nm CMOS model parameters, the optimum frequency range, achieving better than -187.0 dBc/Hz of FoM, can be extended from 6.5-12.5 GHz to 1.5-12.5 GHz. The proposed multiple-divide technique can provide a lower phase-noise, lower power consumption, smaller layout area of LC-VCO.