A Single-Chip 8-Band CMOS Transceiver for 3G Cellular Systems with Digital Interface

Hiroshi YOSHIDA  Takehiko TOYODA  Hiroshi TSURUMI  Nobuyuki ITOH  

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E93-A   No.2   pp.375-381
Publication Date: 2010/02/01
Online ISSN: 1745-1337
DOI: 10.1587/transfun.E93.A.375
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
Category: 
Keyword: 
W-CDMA,  GSM,  3G,  direct conversion,  DC offset,  AGC,  

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Summary: 
In this paper, a single-chip dual-mode 8-band 130 nm CMOS transceiver including A/D/A converters and digital filters with 312 MHz LVDS interface is presented. For a transmitter chain, linear direct quadrature modulation architecture is introduced for both W-CDMA/HSDPA (High Speed Uplink Packet Access) and for GSM/EDGE. Analog baseband LPFs and quadrature modulators are commonly used both for GSM and for EDGE. For a direct conversion receiver chain, ABB (Analog Base-Band) blocks, i.e., LPFs and VGAs, delta-sigma A/D converters, and FIR filters are commonly used for W-CDMA/HSDPA (High Speed Downlink Packet Access) and GSM/EDGE to reduce chip area. Their characteristics can be reconfigured by register-based control sequence. The receiver chain also includes high-speed DC offset cancellers both in analog and in digital stage, and the self-contained AGC controller, whose parameters such as time constant are programmable to be free from DBB (Digital Base-Band) control. The transceiver also includes wide-range VCOs and fractional PLLs, an LVDS driver and receiver for high-speed digital interface of 312 MHz. Measured results reveal that the transceiver satisfies 3GPP specifications for W-CDMA/HSPA (High Speed Packet Access) and GSM/EDGE.