Compact Matched Filter for Integrand Code Using a Real-Valued Shift-Orthogonal Finite-Length Sequence

Takahiro MATSUMOTO  

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E93-A   No.11   pp.2328-2331
Publication Date: 2010/11/01
Online ISSN: 1745-1337
DOI: 10.1587/transfun.E93.A.2328
Print ISSN: 0916-8508
Type of Manuscript: Special Section LETTER (Special Section on Signal Design and its Application in Communications)
Category: Digital Signal Processing
Keyword: 
finite length sequence,  real-valued sequence,  integrand code,  matched filter,  field programmable gate array,  

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Summary: 
In this paper, we proposed the compact construction of a matched filter for integrand code, which do not require the high-rate clock pulse in two-valued PWM (pulse width modulation) code, using a real-valued shift-orthogonal finite-length sequence, which has a sharp aperiodic autocorrelation function with zero sidelobes except at left and right shift-ends. This matched filters are implemented on a field programmable gate array (FPGA) corresponding to 400,000 logic gates. A proposed matched filter for the sequence of length 129 can be constructed by the circuit scale of about 47% compared with conventional filter.