Study-Based Error Recovery Scheme for Networks-on-Chip

Depeng JIN
Shijun LIN
Lieguang ZENG

IEICE TRANSACTIONS on Information and Systems   Vol.E92-D    No.11    pp.2272-2274
Publication Date: 2009/11/01
Online ISSN: 1745-1361
DOI: 10.1587/transinf.E92.D.2272
Print ISSN: 0916-8532
Type of Manuscript: LETTER
Category: VLSI Systems
network-on-chip,  system-on-chip,  error recovery,  

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Motivated by different error characteristics of each path, we propose a study-based error recovery scheme for Networks-on-Chip (NoC). In this scheme, two study processes are executed respectively to obtain the characteristics of the errors in every link first; and then, according to the study results and the selection rule inferred by us, this scheme selects a better error recovery scheme for every path. Simulation results show that compared with traditional simple retransmission scheme and hybrid single-error-correction, multi-error-retransmission scheme, this scheme greatly improves the throughput and cuts down the energy consumption with little area increase.