Energy-Efficient Pre-Execution Techniques in Two-Step Physical Register Deallocation

Kazunaga HYODO  Kengo IWAMOTO  Hideki ANDO  

Publication
IEICE TRANSACTIONS on Information and Systems   Vol.E92-D   No.11   pp.2186-2195
Publication Date: 2009/11/01
Online ISSN: 1745-1361
DOI: 10.1587/transinf.E92.D.2186
Print ISSN: 0916-8532
Type of Manuscript: PAPER
Category: Computer Systems
Keyword: 
microarchitecture,  microprocessor,  instruction pre-execution,  low power,  

Full Text: PDF>>
Buy this Article




Summary: 
Instruction pre-execution is an effective way to prefetch data. We previously proposed an instruction pre-execution scheme, which we call two-step physical register deallocation (TSD). The TSD realizes pre-execution by exploiting the difference between the amount of instruction-level parallelism available with an unlimited number of physical registers and that available with an actual number of physical registers. Although previous TSD study has successfully improved performance, it still has an inefficient energy consumption. This is because attempts are made for instructions to be pre-executed as much as possible, independently of whether or not they can significantly contribute to load latency reduction, allowing for maximal performance improvement. This paper presents a scheme that improves the energy efficiency of the TSD by pre-executing only those instructions that have great benefit. Our evaluation results using the SPECfp2000 benchmark show that our scheme reduces the dynamic pre-executed instruction count by 76%, compared with the original scheme. This reduction saves 7% energy consumption of the execution core with 2% overhead. Performance degrades by 2%, compared with that of the original scheme, but is still 15% higher than that of the normal processor without the TSD.