A 0.31 pJ/Conversion-Step 12-Bit 100 MS/s 0.13 µm CMOS A/D Converter for 3G Communication Systems

Young-Ju KIM  Kyung-Hoon LEE  Myung-Hwan LEE  Seung-Hoon LEE  

IEICE TRANSACTIONS on Electronics   Vol.E92-C   No.9   pp.1194-1200
Publication Date: 2009/09/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E92.C.1194
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Electronic Circuits
ADC,  CMOS,  high resolution,  low voltage,  low power,  cascode compensation,  

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This work describes a 12-bit 100 MS/s 0.13 µm CMOS ADC for 3G wireless communication systems such as two-carrier W-CDMA applications. The proposed ADC employs a four-step pipeline architecture to optimize power consumption and chip area at the target resolution and sampling rate. Area-efficient gate-bootstrapped sampling switches of the input SHA maintain high signal linearity over the Nyquist rate even at a 1.0 V supply. The cascode compensation using a low-impedance feedback path in two-stage amplifiers of the SHA and MDACs achieves the required conversion speed and phase margin with less power consumption and area compared to the Miller compensation. A low-glitch dynamic latch in the sub-ranging flash ADCs reduces kickback noise referred to the input of comparator by isolating the pre-amplifier from the regeneration latch output. The proposed on-chip current and voltage references are based on triple negative TC circuits. The prototype ADC in a 0.13 µm 1P8M CMOS technology demonstrates the measured DNL and INL within 0.38LSB and 0.96LSB at 12-bit, respectively. The ADC shows a maximum SNDR and SFDR of 64.5 dB and 78.0 dB at 100 MS/s, respectively. The ADC with an active die area of 1.22 mm2 consumes 42.0 mW at 100 MS/s and a 1.2 V supply, corresponding to a figure-of-merit of 0.31 pJ/conversion-step.