Low Power 10-b 250 Msample/s CMOS Cascaded Folding and Interpolating A/D Converter

Zhi-Yuan CUI
Yong-Gao JIN
Nam-Soo KIM
Ho-Yong CHOI

IEICE TRANSACTIONS on Electronics   Vol.E92-C    No.8    pp.1073-1079
Publication Date: 2009/08/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E92.C.1073
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Electronic Circuits
A/D converter,  current mirror,  folding,  interpolation,  CMOS process,  

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This paper introduces a new folding amplifier in a folding and interpolating 10-b ADC. The amplifier consists of current mirrors and differential stages. Only one current source is exploited in cascaded differential pairs, which reduces the power consumption significantly. In the folding circuit, the interpolation is implemented with a current division technique. An experiment of the amplifier in 10-b folding signal has been integrated in a single-poly four-metal 0.35 µm CMOS process. The simulation in 10-b folding ADC shows that power consumption is 225 mW at the sampling speed of 250 Msample/s and the power supply of 3.3 V. The preliminary experiment indicates the current steering folder and digital bits operate as expected.