A Low Jitter Self-Calibration PLL for 10-Gbps SoC Transmission Links Application

Kuo-Hsing CHENG
Yu-Chang TSAI
Chien-Nan Jimmy LIU
Kai-Wei HONG
Chin-Cheng KUO

IEICE TRANSACTIONS on Electronics   Vol.E92-C    No.7    pp.964-972
Publication Date: 2009/07/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E92.C.964
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Integrated Electronics
phase-locked loop (PLL),  self-calibration,  low jitter,  multi-phase VCO,  

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A 2.5 GHz 8-phase phase-locked loop (PLL) is proposed for 10-Gbps system on chip (SoC) transmission links application. The proposed PLL has several features which use new design techniques. The first one is a new variable delay cell (VDC) for the voltage control oscillator (VCO). Its advantages over the conventional delay cell are: wide-range output frequency and low noise sensitivity with low KVCO. The second feature is that, the PLL consists of a self-calibration circuit (SCC) which protects the PLL from variations in the process, voltage and temperature (PVT). The third feature is that, the proposed PLL has an 8-phase output frequency and also for avoiding the power/ground (P/G) effect and the substrate noise effect on the PLL, it also has a low jitter output frequency. The PLL is implemented in 0.13-µm CMOS technology. The PLL output jitter is 2.83 ps (rms) less than 0.7% of the output period. The total power dissipation is 21 mW at 2.5 GHz output frequency, and the core area is 0.08 mm2.