A 2.0 Vpp Input, 0.5 V Supply Delta Amplifier with A-to-D Conversion

Yoshihiro MASUI  Takeshi YOSHIDA  Atsushi IWATA  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E92-C   No.6   pp.828-834
Publication Date: 2009/06/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E92.C.828
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
Category: 
Keyword: 
scaled CMOS technology,  voltage mismatch,  DeltAMP,  analog-time-digital conversion (ATD),  

Full Text: PDF>>
Buy this Article




Summary: 
Recent progress in scaled CMOS technologies can enhance signal bandwidth and clock frequency of analog-digital mixed VLSIs. However, the inevitable reduction of supply voltage causes a signal voltage mismatch between a non-scaled analog chip and a scaled A-D mixed chip. To overcome this problem, we present a Delta-Amplifier (DeltAMP) which can handle larger signal amplitude than the supply voltage. DeltaAMP folds a delta signal of an input voltage within a window using a virtual ground amplifier, modulation switches and comparators. For reconstruction of the folded delta signal to the ordinal signal, Analog-Time-Digital conversion (ATD) was also proposed, in which pulse-width analog information obtained at the comparators in DeltAMP was converted to a digital signal by counting. A test chip of DeltAMP with ATD was designed and fabricated using a 90 nm CMOS technology. A 2 Vpp input voltage range and 50 µW power consumption were achieved by the measurements with a 0.5 V supply. High accuracy of 62 dB SNR was obtained at signal bandwidth of 120 kHz.