A 60-GHz Phase-Locked Loop with Inductor-Less Wide Operation Range Prescaler in 90-nm CMOS

Hiroaki HOSHINO  Ryoichi TACHIBANA  Toshiya MITOMO  Naoko ONO  Yoshiaki YOSHIHARA  Ryuichi FUJIMOTO  

IEICE TRANSACTIONS on Electronics   Vol.E92-C   No.6   pp.785-791
Publication Date: 2009/06/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E92.C.785
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
PLL,  synthesizer,  VCO,  ILFD,  phase noise,  

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A 60-GHz phase-locked loop (PLL) with an inductor-less prescaler is fabricated in a 90-nm CMOS process. The inductor-less prescaler has a smaller chip area than previously reported ones. The PLL operates from 61 to 63 GHz and consumes 78 mW from a 1.2 V supply. The phase noise at 100 kHz and 1 MHz offset from carrier are -72 and -80 dBc/Hz, respectively. The prescaler occupies 8040 µm2. The active area of the PLL is 0.31 mm2.