A 150 MS/s 10-bit CMOS Pipelined Subranging ADC with Time Constant Reduction Technique

Xian Ping FAN  Pak Kwong CHAN  Piew Yoong CHEE  

IEICE TRANSACTIONS on Electronics   Vol.E92-C   No.5   pp.719-727
Publication Date: 2009/05/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E92.C.719
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Electronic Circuits
analog-to-digital converter (ADC),  subranging ADC,  pipeline scheme,  CMOS integrated circuit,  switched-capacitor circuit,  CMOS circuit,  

Full Text: PDF>>
Buy this Article

A 150 MS/s 10-bit MOS-inverter-based subranging analog-to-digital converter (ADC) dedicated to a high-speed low-power application is presented in this paper. A new time constant reduction technique is proposed in the multi-stage preamplifier design which aims to further increase the speed of the coarse ADC. A synchronized switch is introduced to minimize the sample-time mismatch in the interleaved architecture of fine ADCs. An internal pipelined scheme incorporating the double sampling and interleaving techniques in fine ADCs allows the ADC sample input signal to run on a consecutive clock, thus maximizing the throughput. The prototype ADC achieves 52 dB SNDR for a 10 MHz input frequency at 150 MS/s. Without calibration, the measured differential nonlinearity (DNL) is 0.5 LSB, while the integral nonlinearity (INL) is 0.9 LSB. The CMOS ADC is fabricated in a 0.35 µm CMOS technology, with an active area of 2.7 mm2, consuming only 178 mW from a single 3 V supply. Comparing technology normalized figure-of-merits, it achieves better power-speed efficiency than other similar types of ADCs.