Design Consideration for Vertical Nonvolatile Memory Device Regarding Gate-Induced Barrier Lowering (GIBL)

Seongjae CHO  Jung Hoon LEE  Gil Sung LEE  Jong Duk LEE  Hyungcheol SHIN  Byung-Gook PARK  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E92-C   No.5   pp.620-626
Publication Date: 2009/05/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E92.C.620
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
Category: 
Keyword: 
3-D nonvolatile memory,  NAND flash memory array,  saturation current,  channel potential barrier,  gate-induced barrier lowering (GIBL),  

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Summary: 
Recently, various types of 3-D nonvolatile memory (NVM) devices have been researched to improve the integration density [1]-[3]. The NVM device of pillar structure can be considered as one of the candidates [4],[5]. When this is applied to a NAND flash memory array, bottom end of the device channel is connected to the bulk silicon. In this case, the current in vertical direction varies depending on the thickness of silicon channel. When the channel is thick, the difference of saturation current levels between on/off states of individual device is more obvious. On the other hand, when the channel is thin, the on/off current increases simultaneously whereas the saturation currents do not differ very much. The reason is that the channel potential barrier seen by drain electrons is lowered by read voltage on the opposite sidewall control gate. This phenomenon that can occur in 3-D structure devices due to proximity can be called gate-induced barrier lowering (GIBL). In this work, the dependence of GIBL on silicon channel thickness is investigated, which will be the criteria in the implementation of reliable ultra-small NVM devices.