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A 0.5 V Area-Efficient Transformer Folded-Cascode CMOS Low-Noise Amplifier
Takao KIHARA Hae-Ju PARK Isao TAKOBE Fumiaki YAMASHITA Toshimasa MATSUOKA Kenji TANIGUCHI
IEICE TRANSACTIONS on Electronics
Publication Date: 2009/04/01
Online ISSN: 1745-1353
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Integrated Electronics
CMOS, low-noise amplifier (LNA), low voltage, transformer,
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A 0.5 V transformer folded-cascode CMOS low-noise amplifier (LNA) is presented. The chip area of the LNA was reduced by coupling the internal inductor with the load inductor, and the effects of the magnetic coupling between these inductors were analyzed. The magnetic coupling reduces the resonance frequency of the input matching network, the peak frequency and magnitude of the gain, and the noise contributions from the common-gate stage to the LNA. A partially-coupled transformer with low magnetic coupling has a small effect on the LNA performance. The LNA with this transformer, fabricated in a 90 nm digital CMOS process, achieved an S11 of -14 dB, NF of 3.9 dB, and voltage gain of 16.8 dB at 4.7 GHz with a power consumption of 1.0 mW at a 0.5 V supply. The chip area of the proposed LNA was 25% smaller than that of the conventional folded-cascode LNA.