Implementation of a Partially Reconfigurable Multi-Context FPGA Based on Asynchronous Architecture

Hasitha Muthumala WAIDYASOORIYA  Masanori HARIYAMA  Michitaka KAMEYAMA  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E92-C   No.4   pp.539-549
Publication Date: 2009/04/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E92.C.539
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Electronic Circuits
Keyword: 
DPGA,  multi-context,  asynchronous FPGA,  

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Summary: 
This paper presents a novel architecture to increase the hardware utilization in multi-context field programmable gate arrays (MC-FPGAs). Conventional MC-FPGAs use dedicated tracks to transfer context-ID bits. As a result, hardware utilization ratio decreases, since it is very difficult to map different contexts, area efficiently. It also increases the context switching power, area and static power of the context-ID tracks. The proposed MC-FPGA uses the same wires to transfer both data and context-ID bits from cell to cell. As a result, programs can be mapped area efficiently by partitioning them into different contexts. An asynchronous multi-context logic block architecture to increase the processing speed of the multiple contexts is also proposed. The proposed MC-FPGA is fabricated using 6-metal 1-poly CMOS design rules. The data and context-ID transfer delays are measured to be 2.03ns and 2.26ns respectively. We achieved 30% processing time reduction for the SAD based correspondance search algorithm.