Enhancements of a Circuit-Level Timing Speculation Technique and Their Evaluations Using a Co-simulation Environment

Yuji KUNITAKE  Kazuhiro MIMA  Toshinori SATO  Hiroto YASUURA  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E92-C   No.4   pp.483-491
Publication Date: 2009/04/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E92.C.483
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Low-Leakage, Low-Voltage, Low-Power and High-Speed Technologies for System LSIs in Deep-Submicron Era)
Category: 
Keyword: 
worst-case design,  timing error,  co-simulation,  parameter variation,  

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Summary: 
A deep submicron semiconductor technology has increased process variations. This fact makes the estimate of the worst-case design margin difficult. In order to realize robust designs, we are investigating such a typical-case design methodology, which we call Constructive Timing Violation (CTV). In the CTV-based design, we can relax timing constraints. However, relaxing timing constraints might cause some timing errors. While we have applied the CTV-based design to a processor, unfortunately, the timing error recovery has serious impact on processor performance. In this paper, we investigate enhancement techniques of the CTV-based design. In addition, in order to accurately evaluate the CTV-based design, we build a co-simulation framework to consider circuit delay at the architectural level. From the co-simulation results, we find the performance penalty is significantly reduced by the enhancement techniques.