Experimental Evaluation of Dynamic Power Supply Noise and Logical Failures in Microprocessor Operations

Mitsuya FUKAZAWA
Masanori KURIMOTO
Rei AKIYAMA
Hidehiro TAKATA
Makoto NAGATA

Publication
IEICE TRANSACTIONS on Electronics   Vol.E92-C    No.4    pp.475-482
Publication Date: 2009/04/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E92.C.475
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Low-Leakage, Low-Voltage, Low-Power and High-Speed Technologies for System LSIs in Deep-Submicron Era)
Category: 
Keyword: 
power supply voltage noise built-in probing circuit,  failure susceptibility,  dynamic frequency scaling,  

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Summary: 
Logical operations in CMOS digital integration are highly prone to fail as the amount of power supply (PS) drop approaches to failure threshold. PS voltage variation is characterized by built-in noise monitors in a 32-bit microprocessor of 90-nm CMOS technology, and related with operation failures by instruction-level programming for logical failure analysis. Combination of voltage drop size and activated logic path determines failure sensitivity and class of failures. Experimental observation as well as simplified simulation is applied for the detailed understanding of the impact of PS noise on logical operations of digital integrated circuits.