Shared Write-Selection Transistor Cell and Leakage-Replication Read Scheme for Large Capacity MRAM Macros

Ryusuke NEBASHI  Noboru SAKIMURA  Tadahiko SUGIBAYASHI  Naoki KASAI  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E92-C   No.4   pp.417-422
Publication Date: 2009/04/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E92.C.417
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Low-Leakage, Low-Voltage, Low-Power and High-Speed Technologies for System LSIs in Deep-Submicron Era)
Category: 
Keyword: 
MRAM,  embedded memory,  SoC,  system LSI,  

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Summary: 
We propose an MRAM macro architecture for SoCs to reduce their area size. The shared write-selection transistor (SWST) architecture is based on 2T1MTJ MRAM cell technology, which enables the same fast access time with a smaller cell area than that of 6T SRAMs. We designed a 4-Mb macro using the SWST architecture with a 0.15-µm CMOS process and a 0.24-µm MRAM process. The macro cell array consists of 81T64MTJ cell array elements, each storing 64 bits of data. The area size is reduced by more than 30%. By introducing a leakage-replication (LR) read scheme, a wide read margin on a test chip is accomplished and 50-ns access time is achieved with SPICE simulation. The 2T1MTJ macro and 81T64MTJ macro can be integrated into a single SoC.