Low-Dynamic-Power and Low-Leakage-Power Techniques for CMOS Square-Root Circuit

Tadayoshi ENOMOTO  Nobuaki KOBAYASHI  

IEICE TRANSACTIONS on Electronics   Vol.E92-C   No.4   pp.409-416
Publication Date: 2009/04/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E92.C.409
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Low-Leakage, Low-Voltage, Low-Power and High-Speed Technologies for System LSIs in Deep-Submicron Era)
clocks,  CMOS digital circuits,  power consumption,  SPICE,  

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A square-root (SR) algorithm, an SR architecture and a leakage current reduction circuit were developed to reduce dynamic power (PAT) and leakage power (PST), while maintaining the speed of a CMOS SR circuit. Using these techniques, a 90-nm CMOS LSI was fabricated. The PAT of the new SR circuit at a clock frequency (fc) of 490 MHz and a supply voltage (VDD) of 0.75 V was 104.1 µW, i.e., 21.6% that (482.3 µW) of a conventional SR circuit. The PST of the new SR circuit was markedly reduced to 19.51 nW, which was only 1.69% that (1,153 nW) of the conventional SR circuit.