On-Chip Memory Power-Cut Scheme Suitable for Low Power SoC Platform

Hiroki SHIMANO  Fukashi MORISHITA  Katsumi DOSAKA  Kazutami ARIMOTO  

IEICE TRANSACTIONS on Electronics   Vol.E92-C    No.3    pp.356-363
Publication Date: 2009/03/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E92.C.356
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Integrated Electronics
power management,  low voltage scalability,  SoC memory platform,  

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The proposed built-in Power-Cut scheme intended for a wide range of dynamically data retaining memories including embedded SoC memories enables the system-level power management to handle SoC on which the several high density and low voltage scalable memory macros are embedded. This scheme handles the deep standby mode in which the SoC memories keep the stored data in the ultra low standby current, and quick recovery to the normal operation mode and precise power management are realized, in addition to the conventional full power-off mode in which the SoC memories stay in the negligibly low standby current but allow the stored data to disappear. The unique feature of the statically or dynamically changeable internal voltages of memory in the deep standby mode brings about much further reduction of the standby current. This scheme will contribute to the further lowering power of the mobile applications requiring larger memory capacity embedded SoC memories.