The ROM Design with Half Grouping Compression Method for Chip Area and Power Consumption Reduction

Ki-Sang JUNG
Kang-Jik KIM
Young-Eun KIM
Jin-Gyun CHUNG
Ki-Hyun PYUN
Jong-Yeol LEE
Hang-Geun JEONG
Seong-Ik CHO

Publication
IEICE TRANSACTIONS on Electronics   Vol.E92-C    No.3    pp.352-355
Publication Date: 2009/03/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E92.C.352
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Integrated Electronics
Keyword: 
ROM,  HG (Half Grouping),  memory,  

Full Text: PDF>>
Buy this Article



Summary: 
In memory design, the issue is smaller size and low power. Most power used in the ROM is consumed in line capacitance such as address lines, word lines, bit lines, and decoder. This paper presents ROM design of a novel HG (Half Grouping) compression method so as to reduce the parasitic capacitance of bit lines and the area of the row decoder for power consumption and chip area reduction. ROM design result of 512 point FFT block shows that the proposed method reduces 40.6% area, 42.12% power, and 37.82% transistor number respectively in comparison with the conventional method. The designed ROM with proposed method is implemented in a 0.35 µm CMOS process. It consumes 5.8 mW at 100 MHz with a single 3.3 V power supply.