Impedance-Isolation Technique for ESD Protection Design in RF Integrated Circuits

Ming-Dou KER  Yuan-Wen HSIAO  

IEICE TRANSACTIONS on Electronics   Vol.E92-C   No.3   pp.341-351
Publication Date: 2009/03/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E92.C.341
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Electronic Components
electrostatic discharge (ESD),  impedance-isolation technique,  LC-tank,  noise figure power gain,  

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An impedance-isolation technique is proposed for on-chip ESD protection design for radio-frequency (RF) integrated circuits (ICs), which has been successfully verified in a 0.25-µm CMOS process with thick top-layer metal. With the resonance of LC-tank at the operating frequency of the RF circuit, the impedance (especially, the parasitic capacitance) of the ESD protection devices can be isolated from the RF input node of low-noise amplifier (LNA). Therefore, the LNA can be co-designed with the proposed impedance-isolation technique to simultaneously achieve excellent RF performance and high ESD robustness. The power gain (S21-parameter) and noise figure of the ESD protection circuits with the proposed impedance-isolation technique have been experimentally measured and compared to those with the conventional double-diodes ESD protection scheme. The proposed impedance-isolation technique had been demonstrated to be suitable for on-chip ESD protection design for RF ICs.