A 5-bit 4.2-GS/s Flash ADC in 0.13-µm CMOS Process

Ying-Zu LIN
Soon-Jyh CHANG
Yen-Ting LIU

IEICE TRANSACTIONS on Electronics   Vol.E92-C    No.2    pp.258-268
Publication Date: 2009/02/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E92.C.258
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Electronic Circuits
flash A/D converter,  high-speed data converter,  interpolation,  resistive averaging network,  

Full Text: FreePDF

This paper investigates and analyzes the resistive averaging network and interpolation technique to estimate the power consumption of preamplifier arrays in a flash analog-to-digital converter (ADC). By comparing the relative power consumption of various configurations, flash ADC designers can select the most power efficient architecture when the operation speed and resolution of a flash ADC are specified. Based on the quantitative analysis, a compact 5-bit flash ADC is designed and fabricated in a 0.13-µm CMOS process. The proposed ADC consumes 180 mW from a 1.2-V supply and occupies 0.16-mm2 active area. Operating at 3.2 GS/s, the ENOB is 4.44 bit and ERBW 1.65 GHz. At 4.2 GS/s, the ENOB is 4.20 bit and ERBW 1.75 GHz. This ADC achieves FOMs of 2.59 and 2.80 pJ/conversion-step at 3.2 and 4.2 GS/s, respectively.