Design of Asynchronous Multi-Bit OTP Memory

Chul-Ho CHOI  Jae-Hyung LEE  Tae-Hoon KIM  Oe-Yong SHIM  Yoon-Geum HWANG  Kwang-Seon AHN  Pan-Bong HA  Young-Hee KIM  

IEICE TRANSACTIONS on Electronics   Vol.E92-C   No.1   pp.173-177
Publication Date: 2009/01/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E92.C.173
Print ISSN: 0916-8516
Type of Manuscript: LETTER
Category: Electronic Circuits
multi-bit OTP,  two-transistor OTP cell,  antifuse,  sense amplifier,  

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We designed an asynchronous multi-bit one-time-programmable (OTP) memory which is useful for micro control units (MCUs) of general mobile devices, automobile appliances, power ICs, display ICs, and CMOS image sensors. A conventional OTP cell consists of an access transistor, a NMOS capacitor as antifuse, and a gate-grounded NMOS diode for electrostatic discharge (ESD) protection to store a single bit per cell. On the contrary, a newly proposed OTP cell consists of a PMOS program transistor, a NMOS read transistor, n NMOS capacitors as antifuses, and n NMOS switches selecting antifuse to store n bits per cell. We used logic supply voltage VDD (=1.5 V) and an external program voltage VPPE (=8.5 V). Also, we simplified the sens amplifier circuit by using the sense amplifier of clocked inverter type [3] instead of the conventional current sens amplifier [2]. The asynchronous multi-bit OTP of 128 bytes is designed with Magnachip 0.13 µm CMOS process. The layout area is 229.52495.78 µm2.