High Gain and Wide Range Time Amplifier Using Inverter Delay Chain in SR Latches

Jaejun LEE  Sungho LEE  Yonghoon SONG  Sangwook NAM  

IEICE TRANSACTIONS on Electronics   Vol.E92-C   No.12   pp.1548-1550
Publication Date: 2009/12/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E92.C.1548
Print ISSN: 0916-8516
Type of Manuscript: LETTER
Category: Electronic Circuits
time amplifier,  time-to-digital converter,  SR latch,  high resolution delay measurement,  all-digital phase-locked loop,  inverter delay chain,  

Full Text: PDF>>
Buy this Article

This paper presents a time amplifier design that improves time resolution using an inverter chain delay in SR latches. Compared with the conventional design, the proposed time amplifier has better characteristics such as higher gain, wide range, and small die size. It is implemented using 0.13 µm standard CMOS technology and the experimental results agree well with the theory.