A Low-Power Reduced Kick-Back Comparator with Improved Calibration for High-Speed Flash ADCs

Guy TORFS  Zhisheng LI  Johan BAUWELINCK  Xin YIN  Jan VANDEWEGE  Geert Van Der PLAS  

IEICE TRANSACTIONS on Electronics   Vol.E92-C   No.10   pp.1328-1330
Publication Date: 2009/10/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E92.C.1328
Print ISSN: 0916-8516
Type of Manuscript: LETTER
Category: Electronic Components
comparator,  kick-back,  calibration,  low-power,  flash ADC,  

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A novel low-power kick-back reduced comparator for use in high-speed flash analog-to-digital converters (ADC) is presented. The proposed comparator combines cascode transistors to reduce the kick-back noise with a built-in threshold voltage to remove the static power consumption of a reference. Without degrading other figures, the kick-back noise is reduced by a factor 8, compared to a previous design without cascode transistors. An improved calibration structure is also proposed to improve linearity when used in an ADC. Simulated in a standard CMOS technology the comparator consumes 106.5 µW at 1.8 V power supply and 1 GHz clock frequency.