A 300 MHz Embedded Flash Memory with Pipeline Architecture and Offset-Free Sense Amplifiers for Dual-Core Automotive Microcontrollers

Shinya KAJIYAMA  Masamichi FUJITO  Hideo KASAI  Makoto MIZUNO  Takanori YAMAGUCHI  Yutaka SHINAGAWA  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E92-C   No.10   pp.1258-1264
Publication Date: 2009/10/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E92.C.1258
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Hardware and Software Technologies on Advanced Microprocessors)
Category: 
Keyword: 
flash memory,  microcontroller,  dual-core,  shared ROM,  pipeline,  sense amplifier,  

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Summary: 
A novel 300 MHz embedded flash memory for dual-core microcontrollers with a shared ROM architecture is proposed. One of its features is a three-stage pipeline read operation, which enables reduced access pitch and therefore reduces performance penalty due to conflict of shared ROM accesses. Another feature is a highly sensitive sense amplifier that achieves efficient pipeline operation with two-cycle latency one-cycle pitch as a result of a shortened sense time of 0.63 ns. The combination of the pipeline architecture and proposed sense amplifiers significantly reduces access-conflict penalties with shared ROM and enhances performance of 32-bit RISC dual-core microcontrollers by 30%.