Synthesis and Design of Parameter Extractors for Low-Power Pre-Computation-Based Content-Addressable Memory

Shanq-Jang RUAN  Jui-Yuan HSIEH  Chia-Han LEE  

IEICE TRANSACTIONS on Electronics   Vol.E92-C   No.10   pp.1249-1257
Publication Date: 2009/10/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E92.C.1249
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Hardware and Software Technologies on Advanced Microprocessors)
content-addressable memory (CAM),  pre-computation-based CAM (PB-CAM),  low-power,  synthesis,  CAM cell design,  

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This paper presents a gate-block selection algorithm, which can synthesize a proper parameter extractor of the pre-computation-based content-addressable memory (PB-CAM) to enhance power efficiency for specific applications such as embedded systems, microprocessor and SOC, etc. Furthermore, a novel CAM cell design with single bit-line is proposed. The proposed CAM cell design requires only one heavy loading bit-line and merely is constructed with eight transistors. The whole PB-CAM design was described in Spice with TSMC 0.35 µm double-poly quadruple-metal CMOS process. We used Synopsys Nanosim to estimate power consumption. With a 128 words by 32 bits CAM size, the experimental results showed that our proposed PB-CAM effectively reduces 18.21% of comparison operations in the CAM and saves 16.75% in power reduction by synthesizing a proper parameter extractor of the PB-CAM compared with the 1's count PB-CAM. This implies that our proposed PB-CAM is more flexible and adaptive for specific applications.