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Analysis of Path Delay Fault Testability for Two-Rail Logic Circuits
Kazuteru NAMBA Hideo ITO
Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Vol.E92-A
No.9
pp.2295-2303 Publication Date: 2009/09/01 Online ISSN: 1745-1337
DOI: 10.1587/transfun.E92.A.2295 Print ISSN: 0916-8508 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: two-rail logic circuit, path delay fault, testability, functional sensitizability, over-testing,
Full Text: PDF(447.9KB)>>
Summary:
The importance of redundant technologies for improving dependability and delay fault testability are growing. This paper presents properties of a class of redundant technologies, namely two-rail logic, and analyzes testability of path delay faults occurring on two-rail logic circuits. The paper reveals the following characteristics of two-rail logic circuits: While the number of paths in two-rail logic circuits is twice that in ordinary single-rail logic circuits, the number of robust testable path delay faults in two-rail logic circuits is twice or more that in the single-rail logic circuits. This suggests two-rail logic circuits are more testable than ordinary single-rail logic circuits. On two-rail logic circuits, there may be some robust testable path delay faults that are functional un-sensitizable for any input vectors consisting of codewords of two-rail codes, i.e. for any input vectors that can occur during fault-free operation. Even if such faults occur, the circuits are still strongly fault secure for unidirectional stuck-at faults as well as they work correctly.
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