
For FullText PDF, please login, if you are a member of IEICE,
or go to Pay Per View on menu list, if you are a nonmember of IEICE.

A CMOS Spiking Neural Network Circuit with Symmetric/Asymmetric STDP Function
Hideki TANAKA Takashi MORIE Kazuyuki AIHARA
Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Vol.E92A
No.7
pp.16901698 Publication Date: 2009/07/01 Online ISSN: 17451337
DOI: 10.1587/transfun.E92.A.1690 Print ISSN: 09168508 Type of Manuscript: PAPER Category: Neural Networks and Bioengineering Keyword: spiking neuron model, associative memory, spiketiming dependent synaptic plasticity (STDP), LSI implementation,
Full Text: PDF>>
Summary:
In this paper, we propose an analog CMOS circuit which achieves spiking neural networks with spiketiming dependent synaptic plasticity (STDP). In particular, we propose a STDP circuit with symmetric function for the first time, and also we demonstrate associative memory operation in a Hopfieldtype feedback network with STDP learning. In our spiking neuron model, analog information expressing processing results is given by the relative timing of spike firing events. It is well known that a biological neuron changes its synaptic weights by STDP, which provides learning rules depending on relative timing between asynchronous spikes. Therefore, STDP can be used for spiking neural systems with learning function. The measurement results of fabricated chips using TSMC 0.25 µm CMOS process technology demonstrate that our spiking neuron circuit can construct feedback networks and update synaptic weights based on relative timing between asynchronous spikes by a symmetric or an asymmetric STDP circuits.

