Design of Low Power QPP Interleave Address Generator Using the Periodicity of QPP

Won-Ho LEE  Chong Suck RIM  

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E92-A   No.6   pp.1538-1540
Publication Date: 2009/06/01
Online ISSN: 1745-1337
DOI: 10.1587/transfun.E92.A.1538
Print ISSN: 0916-8508
Type of Manuscript: LETTER
Category: VLSI Design Technology and CAD
QPP,  interleaver,  low power design,  turbo decoder,  address generator,  

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This paper presents two power-saving designs for Quadratic Polynomial Permutation (QPP) interleave address generator of which interleave length K is fixed and unfixed, respectively. These designs are based on our observation that the quadratic term f2x2%K of f(x) = (f1x+f2x2)%K, which is the QPP address generating function, has a short period and is symmetric within the period. Power consumption is reduced by 27.4% in the design with fixed-K and 5.4% in the design with unfixed-K on the average for various values of K, when compared with existing designs.