Improvement in Computational Accuracy of Output Transition Time Variation Considering Threshold Voltage Variations

Takaaki OKUMURA  Atsushi KUROKAWA  Hiroo MASUDA  Toshiki KANAMOTO  Masanori HASHIMOTO  Hiroshi TAKAFUJI  Hidenari NAKASHIMA  Nobuto ONO  Tsuyoshi SAKATA  Takashi SATO  

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E92-A    No.4    pp.990-997
Publication Date: 2009/04/01
Online ISSN: 1745-1337
DOI: 10.1587/transfun.E92.A.990
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on Advanced Technologies Emerging Mainly from the 21st Workshop on Circuits and Systems in Karuizawa)
SSTA,  output,  transition time,  gate delay model,  process variation,  

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Process variation is becoming a primal concern in timing closure of LSI (Large Scale Integrated Circuit) with the progress of process technology scaling. To overcome this problem, SSTA (Statistical Static Timing Analysis) has been intensively studied since it is expected to be one of the most efficient ways for performance estimation. In this paper, we study variation of output transition-time. We firstly clarify that the transition-time variation can not be expressed accurately by a conventional first-order sensitivity-based approach in the case that the input transition-time is slow and the output load is small. We secondly reveal quadratic dependence of the output transition-time to operating margin in voltage. We finally propose a procedure through which the estimation of output transition-time becomes continuously accurate in wide range of input transition-time and output load combinations.