Technique to Improve the Performance of Time-Interleaved A-D Converters with Mismatches of Non-linearity

Koji ASAMI  Takahide SUZUKI  Hiroyuki MIYAJIMA  Tetsuya TAURA  Haruo KOBAYASHI  

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E92-A   No.2   pp.374-380
Publication Date: 2009/02/01
Online ISSN: 1745-1337
DOI: 10.1587/transfun.E92.A.374
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
Category: 
Keyword: 
time-interleaved A-D converters,  non-linearity,  foreground calibration,  digital error correction,  automatic test equipment,  

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Summary: 
One method for achieving high-speed waveform digitizing uses time-interleaved A-D Converters (ADCs). It is known that, in this method, using multiple ADCs enables sampling at a rate higher than the sampling rate of the ADC being used. Degradation of the dynamic range, however, results from such factors as phase error in the sampling clock applied to the ADC, and mismatched frequency characteristics among the individual ADCs. This paper describes a method for correcting these mismatches using a digital signal processing (DSP) technique for automatic test equipment applications. This method can be applied to any number of interleaved ADCs, and it does not require any additional hardware; good correction and improved accuracy can be obtained simply by adding a little to the computing overhead.