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Low-Power Embedded Processor Design Using Branch Direction
Gi-Ho PARK Jung-Wook PARK Gunok JUNG Shin-Dug KIM
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/12/01
Online ISSN: 1745-1337
Print ISSN: 0916-8508
Type of Manuscript: Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
low power, BTB, wordline gating,
Full Text: PDF(344.2KB)>>
This paper presents a wordline gating logic for reducing unnecessary BTB accesses. Partial bit of the branch predictor was simultaneously recorded in the middle of BTB to prevent further SRAM operation. Experimental results with embedded applications showed that the proposed mechanism reduces around 38% of BTB power consumption.