IEICE Trans - An Approach for Reducing Leakage Current Variation due to Manufacturing Variability

An Approach for Reducing Leakage Current Variation due to Manufacturing Variability

Tsuyoshi SAKATA  Takaaki OKUMURA  Atsushi KUROKAWA  Hidenari NAKASHIMA  Hiroo MASUDA  Takashi SATO  Masanori HASHIMOTO  Koutaro HACHIYA  Katsuhiro FURUKAWA  Masakazu TANAKA  Hiroshi TAKAFUJI  Toshiki KANAMOTO

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E92-A   No.12   pp.3016-3023
Publication Date: 2009/12/01
Online ISSN: 1745-1337
DOI: 10.1587/transfun.E92.A.3016
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Device and Circuit Modeling and Analysis
Keyword:
low power,  leakage,  gate delay model,  variation,

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Summary:
Leakage current is an important qualitative metric of LSI (Large Scale Integrated circuit). In this paper, we focus on reduction of leakage current variation under the process variation. Firstly, we derive a set of quadratic equations to evaluate delay and leakage current under the process variation. Using these equations, we discuss the cases of varying leakage current without degrading delay distribution and propose a procedure to reduce the leakage current variations. From the experiments, we show the proposed method effectively reduces the leakage current variation up to 50% at 90 percentile point of the distribution compared with the conventional design approach.