Reducing Interconnect Complexity for Efficient Path Metric Memory Management in Viterbi Decoders

Ming-Der SHIEH  Tai-Ping WANG  Chien-Ming WU  

Publication
IEICE TRANSACTIONS on Information and Systems   Vol.E91-D   No.9   pp.2300-2311
Publication Date: 2008/09/01
Online ISSN: 1745-1361
DOI: 10.1093/ietisy/e91-d.9.2300
Print ISSN: 0916-8532
Type of Manuscript: PAPER
Category: VLSI Systems
Keyword: 
Viterbi decoder (VD),  in-place scheduling,  path metric memory management,  VLSI architecture,  

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Summary: 
We present a systematic and efficient way of managing the path metric memory and simplifying its connection network to the add_compare_select unit (ACSU) for Viterbi decoder (VD) design. Using the derived equations for memory partition and add-compare-select (ACS) arrangement together with the extended in-place scheduling scheme proposed in this work, we can increase the memory bandwidth for conflict-free path metric accesses with hardwired interconnection between the path metric memory and ACSU. Compared with the existing work, the developed architecture possesses the following advantages: (1) Each partitioned memory bank can be treated as a local memory of a specific processing element, inside the ACSU, with hardwired interconnection, so that the interconnect complexity is reduced significantly. (2) The partitioned memory banks can be merged into only two pseudo-banks regardless of the number of adopted ACS processing elements. This not only greatly simplifies the design of address generation unit, but also makes smaller the physical size of required memory. (3) The implementation can be accomplished in a systematic way with regular and simple controlling circuitry. Experimental results demonstrate the effectiveness of the developed architecture and the benefit will be more apparent for convolutional codes with large memory order.