A Novel Hardware Architecture of Intra-Predictor Generator for H.264/AVC Codec

Sanghoon KWAK  Jinwook KIM  Dongsoo HAR  

Publication
IEICE TRANSACTIONS on Information and Systems   Vol.E91-D   No.7   pp.2083-2086
Publication Date: 2008/07/01
Online ISSN: 1745-1361
DOI: 10.1093/ietisy/e91-d.7.2083
Print ISSN: 0916-8532
Type of Manuscript: LETTER
Category: Image Processing and Video Processing
Keyword: 
H.264/AVC,  intra predictor,  hardware implementation,  architecture level optimization,  

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Summary: 
The intra-prediction unit is an essential part of H.264 codec, since it reduces the amount of data to be encoded by predicting pixel values (luminance and chrominance) from their neighboring blocks. A dedicated hardware implementation for the intra-prediction unit is required for real-time encoding and decoding of high resolution video data. To develop a cost-effective intra-prediction unit this paper proposes a novel architecture of intra-predictor generator, the core part of intra-prediction unit. The proposed intra-predictor generator enables the intra-prediction unit to achieve significant clock cycle reduction with approximately the same gate count, as compared to Huang's work [3].