Efficient VLSI Design of Residue-to-Binary Converter for the Moduli Set (2n, 2n+1 - 1, 2n - 1)

Su-Hon LIN  Ming-Hwa SHEU  Chao-Hsiang WANG  

IEICE TRANSACTIONS on Information and Systems   Vol.E91-D   No.7   pp.2058-2060
Publication Date: 2008/07/01
Online ISSN: 1745-1361
DOI: 10.1093/ietisy/e91-d.7.2058
Print ISSN: 0916-8532
Type of Manuscript: LETTER
Category: Computer Systems
residue number system (RNS),  residue-to-binary converter,  moduli set,  VLSI design,  

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The moduli set (2n, 2n+1-1, 2n-1) which is free of (2n+1)-type modulus is profitable to construct a high-performance residue number system (RNS). In this paper, we derive a reduced-complexity residue-to-binary conversion algorithm for the moduli set (2n, 2n+1-1, 2n-1) by using New Chinese Remainder Theorem (CRT). The resulting converter architecture mainly consists of simple adder and multiplexer (MUX) which is suitable to realize an efficient VLSI implementation. For the various dynamic range (DR) requirements, the experimental results show that the proposed converter can significantly achieve at least 23.3% average Area-Time (AT) saving when comparing with the latest designs. Based on UMC 0.18 µm CMOS cell-based technology, the chip area for 16-bit residue-to-binary converter is 931931 µm2 and its working frequency is about 135 MHz including I/O pad.