IEICE Trans - Post-BIST Fault Diagnosis for Multiple Faults

Post-BIST Fault Diagnosis for Multiple Faults

Hiroshi TAKAHASHI  Yoshinobu HIGAMI  Shuhei KADOYAMA  Yuzo TAKAMATSU  Koji YAMAZAKI  Takashi AIKYO  Yasuo SATO

Publication
IEICE TRANSACTIONS on Information and Systems   Vol.E91-D   No.3   pp.771-775
Publication Date: 2008/03/01
Online ISSN: 1745-1361
DOI: 10.1093/ietisy/e91-d.3.771
Print ISSN: 0916-8532
Type of Manuscript: Special Section LETTER (Special Section on Test and Verification of VLSIs)
Category:
Keyword:
post-BIST fault diagnosis,  multiple stuck-at faults,  combinational circuits,  pass/fail information,

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Summary:
With the increasing complexity of LSI, Built-In Self Test (BIST) is a promising technique for production testing. We herein propose a method for diagnosing multiple stuck-at faults based on the compressed responses from BIST. We refer to fault diagnosis based on the ambiguous test pattern set obtained by the compressed responses of BIST as post-BIST fault diagnosis [1]. In the present paper, we propose an effective method by which to perform post-BIST fault diagnosis for multiple stuck-at faults. The efficiency of the success ratio and the feasibility of diagnosing large circuits are discussed.