Design for Testability Method to Avoid Error Masking of Software-Based Self-Test for Processors

Masato NAKAZATO  Michiko INOUE  Satoshi OHTAKE  Hideo FUJIWARA  

IEICE TRANSACTIONS on Information and Systems   Vol.E91-D   No.3   pp.763-770
Publication Date: 2008/03/01
Online ISSN: 1745-1361
DOI: 10.1093/ietisy/e91-d.3.763
Print ISSN: 0916-8532
Type of Manuscript: Special Section PAPER (Special Section on Test and Verification of VLSIs)
Category: High-Level Testing
software-based self-test,  processor,  test program template,  design for testability,  error masking,  at-speed testing,  

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In this paper, we propose a design for testability method for test programs of software-based self-test using test program templates. Software-based self-test using templates has a problem of error masking where some faults detected in a test generation for a module are not detected by the test program synthesized from the test. The proposed method achieves 100% template level fault efficiency, that is, it completely avoids the error masking. Moreover, the proposed method has no performance degradation (adds only observation points) and enables at-speed testing.