A Self-Test of Dynamically Reconfigurable Processors with Test Frames

Tomoo INOUE  Takashi FUJII  Hideyuki ICHIHARA  

IEICE TRANSACTIONS on Information and Systems   Vol.E91-D   No.3   pp.756-762
Publication Date: 2008/03/01
Online ISSN: 1745-1361
DOI: 10.1093/ietisy/e91-d.3.756
Print ISSN: 0916-8532
Type of Manuscript: Special Section PAPER (Special Section on Test and Verification of VLSIs)
Category: High-Level Testing
dynamically reconfigurable processors,  self-test,  optimal contexts,  test application time,  test frames,  

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This paper proposes a self-test method of coarse grain dynamically reconfigurable processors (DRPs) without hardware overhead. In the method, processor elements (PEs) compose a test frame, which consists of test pattern generators (TPGs), processor elements under test (PEUTs) and response analyzers (RAs), while testing themselves one another by changing test frames appropriately. We design several test frames with different structures, and discuss the relationship of the structures to the numbers of contexts and test frames for testing all the functions of PEs. A case study shows that there exists an optimal test frame which minimizes the test application time under a constraint.