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Scheduling Power-Constrained Tests through the SoC Functional Bus
Fawnizu Azmadi HUSSIN Tomokazu YONEDA Alex ORAILOLU Hideo FUJIWARA
IEICE TRANSACTIONS on Information and Systems
Publication Date: 2008/03/01
Online ISSN: 1745-1361
Print ISSN: 0916-8532
Type of Manuscript: Special Section PAPER (Special Section on Test and Verification of VLSIs)
Category: High-Level Testing
functional bus, functional TAM, power-constrained, packet-based scheduling, system-on-chip testing,
Full Text: PDF(810.6KB)>>
This paper proposes a test methodology for core-based testing of System-on-Chips by utilizing the functional bus as a test access mechanism. The functional bus is used as a transportation channel for the test stimuli and responses from a tester to the cores under test (CUT). To enable test concurrency, local test buffers are added to all CUTs. In order to limit the buffer area overhead while minimizing the test application time, we propose a packet-based scheduling algorithm called PAcket Set Scheduling (PASS), which finds the complete packet delivery schedule under a given power constraint. The utilization of test packets, consisting of a small number of bits of test data, for test data delivery allow an efficient sharing of bus bandwidth with the help of an effective buffer-based test architecture. The experimental results show that the methodology is highly effective, especially for smaller bus widths, compared to previous approaches that do not use the functional bus.