Test Data Compression for Scan-Based BIST Aiming at 100x Compression Rate

Masayuki ARAI  Satoshi FUKUMOTO  Kazuhiko IWASAKI  Tatsuru MATSUO  Takahisa HIRAIDE  Hideaki KONISHI  Michiaki EMORI  Takashi AIKYO  

IEICE TRANSACTIONS on Information and Systems   Vol.E91-D   No.3   pp.726-735
Publication Date: 2008/03/01
Online ISSN: 1745-1361
DOI: 10.1093/ietisy/e91-d.3.726
Print ISSN: 0916-8532
Type of Manuscript: Special Section PAPER (Special Section on Test and Verification of VLSIs)
Category: Test Compression
test data compression,  test response compaction,  BIST-aided scan test,  X-value,  ATPG,  

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We developed test data compression scheme for scan-based BIST, aiming to compress test stimuli and responses by more than 100 times. As scan-BIST architecture, we adopt BIST-Aided Scan Test (BAST), and combines four techniques: the invert-and-shift operation, run-length compression, scan address partitioning, and LFSR pre-shifting. Our scheme achieved a 100x compression rate in environments where Xs do not occur without reducing the fault coverage of the original ATPG vectors. Furthermore, we enhanced the masking logic to reduce data for X-masking so that test data is still compressed to 1/100 in a practical environment where Xs occur. We applied our scheme to five real VLSI chips, and the technique compressed the test data by 100x for scan-based BIST.