Fault Simulation and Test Generation for Transistor Shorts Using Stuck-at Test Tools

Yoshinobu HIGAMI
Kewal K. SALUJA
Hiroshi TAKAHASHI
Shin-ya KOBAYASHI
Yuzo TAKAMATSU

Publication
IEICE TRANSACTIONS on Information and Systems   Vol.E91-D    No.3    pp.690-699
Publication Date: 2008/03/01
Online ISSN: 1745-1361
DOI: 10.1093/ietisy/e91-d.3.690
Print ISSN: 0916-8532
Type of Manuscript: Special Section PAPER (Special Section on Test and Verification of VLSIs)
Category: Defect-Based Testing
Keyword: 
transistor short,  fault simulation,  test generation,  stuck-at test tool,  

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Summary: 
This paper presents methods for detecting transistor short faults using logic level fault simulation and test generation. The paper considers two types of transistor level faults, namely strong shorts and weak shorts, which were introduced in our previous research. These faults are defined based on the values of outputs of faulty gates. The proposed fault simulation and test generation are performed using gate-level tools designed to deal with stuck-at faults, and no transistor-level tools are required. In the test generation process, a circuit is modified by inserting inverters, and a stuck-at test generator is used. The modification of a circuit does not mean a design-for-testability technique, as the modified circuit is used only during the test generation process. Further, generated test patterns are compacted by fault simulation. Also, since the weak short model involves uncertainty in its behavior, we define fault coverage and fault efficiency in three different way, namely, optimistic, pessimistic and probabilistic and assess them. Finally, experimental results for ISCAS benchmark circuits are used to demonstrate the effectiveness of the proposed methods.